| Name | Description |
|---|---|
| Adc | Adc instruction: Add with Carry |
| Add | Add instruction: Add ARMv6-M provides register and small immediate versions only. |
| Adr | Adr instruction: Form PC-relative Address First operand is the PC. Second operand is an immediate constant. |
| And | And instruction: Bitwise AND |
| Asr | Asr instruction: Arithmetic Shift Right |
| B | B instruction: Branch to target address |
| Bic | Bic instruction: Bitwise Bit Clear |
| Bkpt | Bkpt instruction: Breakpoint instruction It can cause a running system to halt depending on the debug configuration. |
| Bl | Bl instruction: Call a subroutine |
| Blx | Blx instruction: Call a subroutine |
| Bx | Bx instruction: Branch to target address |
| Cmn | Cmn instruction: Compare Negative Sets flags. Like ADD but with no destination register. |
| Cmp | Cmp instruction: Compare Sets flags. Like SUB but with no destination register. |
| Dmb | Dmb instruction: Data Memory Barrier |
| Dsb | Dsb instruction: Data Synchronization Barrier |
| Eor | Eor instruction: Bitwise Exclusive OR |
| Isb | Isb instruction: Instruction Synchronization Barrier |
| Ldm | Ldm instruction: Load Multiple |
| Ldmfd | Ldmfd instruction: Load Multiple Full Descending |
| Ldmia | Ldmia instruction: Load Multiple Increment After |
| Ldr | Ldr instruction: Load 32-bit word Load and store instructions |
| Ldrb | Ldrb instruction: Load 8-bit unsigned byte Load and store instructions |
| Ldrh | Ldrh instruction: Load 16-bit unsigned halfword Load and store instructions |
| Ldrsb | Ldrsb instruction: Load 8-bit signed byte Load and store instructions |
| Ldrsh | Ldrsh instruction: Load 16-bit signed halfword Load and store instructions |
| Lsl | Lsl instruction: Logical Shift Left |
| Lsr | Lsr instruction: Logical Shift Right |
| Mov | Mov instruction: Copies operand to destination "Has only one operand. Constant support is limited to loading an 8-bit immediate value in ARMv6-M. If the operand is a shifted register, the instruction is an LSL, LSR, ASR, or ROR instruction instead." |
| Msr | Msr instruction: "move the contents of the Application Program Status Register, APSR, to or from a general-purpose register." Status register access instructions |
| Mul | Mul instruction: Performs a 32x32 multiply that generates a 32-bit result.The instruction can operate on signed or unsigned quantities. |
| Mvn | Mvn instruction: Bitwise NOT Has only one operand. ARMv6-M does not support any immediate or shift options. |
| Nop | Nop instruction: No Operation |
| Orr | Orr instruction: Bitwise OR |
| Pop | Pop instruction: Pop multiple registers off the stack |
| Push | Push instruction: Push multiple registers onto the stack This instruction decrements the base register before the memory access and updates the base register. |
| Rev | Rev instruction: Byte-Reverse Word |
| Rev16 | Rev16 instruction: Byte-Reverse Packed Halfword |
| Revsh | Revsh instruction: Byte-Reverse Signed Halfword |
| Ror | Ror instruction: Rotate Right |
| Rsb | Rsb instruction: Reverse Subtract Subtracts first operand from second operand. ARMv6-M only supports an immediate value of 0. |
| Rsc | Rsc instruction: Reverse Subtract Carry Subtracts second operand from first operand plus carry minus 1. ARMv6-M only supports an immediate value of 0. |
| Sbc | Sbc instruction: Subtract with Carry |
| Sev | Sev instruction: Send Event |
| Stm | Stm instruction: Store Multiple |
| Stmea | Stmea instruction: Store Multiple Empty Ascending |
| Stmia | Stmia instruction: Store Multiple Increment After |
| Str | Str instruction: Store 32-bit word Load and store instructions |
| Strb | Strb instruction: Store 8-bit byte Load and store instructions |
| Strh | Strh instruction: Store 16-bit halfword Load and store instructions |
| Sub | Sub instruction: Subtract |
| Svc | Svc instruction: Supervisor Call |
| Swi | Swi instruction: Instruction is used to cause an SVCall (The Supervisor Call) exception to occur |
| Sxtb | Sxtb instruction: Signed Extend Byte Extend 8 bits to 32 |
| Sxth | Sxth instruction: Signed Extend Halfword Extend 16 bits to 32 |
| Teq | Teq instruction: Test Sets flags. Like EOR but with no destination register. |
| Tst | Tst instruction: Test Sets flags. Like AND but with no destination register. |
| Uxtb | Uxtb instruction: Unsigned Extend Byte Extend 8 bits to 32 |
| Uxth | Uxth instruction: Unsigned Extend Halfword Extend 16 bits to 32 |
| Wfe | Wfe instruction: Wait for Event |
| Wfi | Wfi instruction: Wait for Interrupt |
| Yield | Yield instruction: Yield |